When forming a CMOS device, a gate structure is often formed on a substrate, followed by forming trenches in the substrate on both sides of the gate structure. Stress layers are formed in the trenches and then are doped to form source/drain regions. However, overfill may occur to the stress layers to have a top surface protruding above a top surface of the substrate.
Such overfill of the stress layers may generate uneven surface of the substrate and thus impede subsequent manufacturing processes. In addition, overfill of the stress layers may affect stress distribution in the stress layers, e.g., may weaken or remove desired stress to be generated in the stress layers. Device performance of the resultant CMOS devices may be adversely affected.
Conventional solutions to solve the overfill problems include use of an etch process to remove overfill portion of the stress layers above the top surface of the substrate. However, a single wafer may include a large amount of CMOS devices with different sizes. Accordingly, distances or pitches between trenches in such different CMOS devices are also different. The overfill portions may have different heights over corresponding stress layers for trenches having different sizes. Consequently, it is difficult to control the etch process of the overfill portions with different heights for various different CMOS devices on a same wafer.
When etching the overfill portions with different heights on a same wafer, the stress layers after etching may still have different heights over the substrate surface for the various CMOS devices on the same wafer. For example, some stress layers of some CMOS devices may be etched to reach a desired height, e.g., to be substantially flat with the substrate surface, while other stress layers of other CMOS devices in the same wafer may be etched still having a height over/below the substrate surface due to unsufficient/over etching.
Therefore, it is desirable to control an etching process of stress layers on a wafer, such that overfilling portions of stress layers can be removed and, after etching, all stress layers in a same wafer can be substantially flush with the substrate surface.